Use of (first in first out) FIFO memory registers in digital designs for buffering and flow control has been widespread for many years. The emergence of system on chip (SOC) and networks on chip (NOC) for internal connections have made it imperative to ensure correct flow of data across the chip or die. The various computing components in such networks are often synchronized on different clocks. Thus data transfer in such systems requires an asynchronous first in first out (FIFO) register to assist in transferring data between differently clocked components.
An asynchronous FIFO refers to a FIFO design where data values are written sequentially into a FIFO buffer using one clock domain, and the data values are sequentially read from the same FIFO buffer using another clock domain, where the two clock domains are asynchronous to each other. The first in first out (FIFO) buffer serves as a memory buffer between two asynchronous devices each with simultaneous write and read access to and from the FIFO. The accesses are independent of one another. Data written into a FIFO is sequentially read out in a pipelined manner. Thus the first data word written into a FIFO will be the first data word that is read out. The fundamental architecture of a FIFO has a write port, a read port, and memory locations. Each port has its own associated pointer that points to a location in memory. After a reset, both write and read pointers will be at the first memory location within the FIFO where the memory registers are empty. When the write address register again reaches the read address register, the FIFO registers are full. Every write operation will cause the write pointer to increment to the next address in memory thus filling registers, while every read operation will increment the read pointer to the next memory location as each register is emptied.
In order to synchronize read and write operations, a synchronizer circuit is used for the comparison of the addresses of the pointers. Such a comparison will determine whether the FIFO is empty or full and thus whether either read or write operations may be performed respectively. A synchronizer includes logic devices such as flip flops that compare the addresses of data on the read and write side. Such circuits trade off latency for reliability. Reliability requires more stages of flip flop circuits, but increases the latency of the synchronization since the address comparisons must flow through each flip flop stage. In a conventional FIFO, the status signals (or addresses from which they are generated) must pass through synchronizers before usage in the receiving clock domain. The stage count in these synchronizers determines their latency/reliability trade-off.
One common technique for designing an asynchronous FIFO is to use Gray code pointers that are synchronized into the opposite clock domain before generating synchronous FIFO full or empty status signals. One Gray code counter style uses a single set of flip-flops as the Gray code register. While transferring pointer information between independent clock domains in an asynchronous FIFO, each bit, new or old of the pointer, needs to be sent. If more than one bit in the multi-bit pointer is changing at the sampling point, an incorrect binary value can be propagated. By guaranteeing that only one bit can be changing, Gray codes guarantee that the only possible sampled values are the new or old multi-bit value, ensuring reliable flag information indicating whether the read and write registers are full or empty.
This design requires a multi-bit synchronizer in each port, to make the other port's address register usable. This synchronizer is large, since many bits need to be simultaneously synchronized, and these bits may need to be converted to and from Gray code in order for the synchronization to be well-behaved. This synchronizer also sits in a fixed location in the design, resulting in a fixed latency/reliability tradeoff. This tradeoff is a consequence of the fact that the more time a synchronizer has, the more latency it injects into the surrounding system, and the more reliable is its operation.